1. Field of the Invention
The present invention relates to design of semiconductor memory circuits. More particularly, it relates to a buffer amplifier architecture for buffering signals that are supplied in parallel to identical chips on a semiconductor circuit module, particularly DRAM chips on a DRAM memory module.
2. Background Information
In semiconductor memory modules, for example DRAM memory modules, which are clocked at ever higher frequencies, it is paramount that signals supplied to a group of identical chips in parallel, such as address, command and data signals, should have the same signal propagation time to the extent possible. In this context, the delay time range of registers and buffer amplifier architectures that are used in conventional semiconductor memory modules provided with registers is frequently too high. The delay time typically ranges from 0.9 ns to 2.5 ns. As a result, at frequencies above 100 mHz, the time tolerances of the signals on the command/address bus are very narrow. Typically, this has been compensated for by a register delay using an adjustable clock delay. The setting of a clock delay, once made, is then fixed and does not adapt to different characteristics of the semiconductor circuit module. The inability to change the clock delay may be undesirable in certain applications.